Warm Electronics and Flight Software
The warm electronics are shared with the IRS. These combined electronics provide circuitry for control of the three detector arrays, the scan mirror, and other cold instrument functions. In addition, they digitize the science and housekeeping signals and include a RAD6000 processor for data processing and formatting. The RAD6000 also receives commands from the spacecraft computer and sends formatted science and engineering data to it for compression and telemetry to Earth.
Electronics
The MIPS/IRS warm electronics are designed to be standby redundant; that is, two identical electronics boxes are flown; both boxes are connected to the arrays and scan mirror in the cold instrument, but only one box is powered at a time. The electronics are housed in two identical ten slot chassis. The outside dimensions of each enclosure are approximately 340mm x 320mm x 204mm and the weight of each populated box is about 20Kg. Power dissipation of the electronics is expected to be about 64 watts. The electronics enclosure is designed to provide radiation shielding of the electronic components. The components themselves are radiation hardened. The diagram below shows
the overall structure of the electronics.
A total of 40 identical analog chains (see on the right) are provided in the MIPS warm electronics for the two Ge FPAs: 32 for the 70mm FPA and 8 for the 160mm one. The cable connecting the FPA outputs to the MIPS warm electronics is over three meters long. Since this cable is routed from the 1.5K instrument out to the 300K warm electronics box, a low thermal conductivity wire is used for these conductors. Each cable contains 24 pairs of twisted pair manganin wire protected by an outer shield; 
each output signal is twisted with a complementary ground reference. The total capacitance of up to 700pF must be driven by the array output amplifiers. An instrumentation amplifier in the warm electronics, which helps reject common mode noise on the incoming signal and ground reference lines, receives the signals. The output of the instrumentation amplifier is summed with a DC offset voltage and then fed into a 1KHz two pole filter. The bandwidth of this filter was chosen to be low enough to limit the FPA noise bandwidth and yet provide a reasonable readout time for the FPA. The outputs of the 40 analog chains are multiplexed down to a single analog line, which is fed to the analog to digital converter (ADC) as shown in Figure 6. A 16 bit ADC is used to digitize the processed pixel data from the germanium FPAs. The overall Ge FPA signal chain has a gain of 7x. Only 14 bits of the available 16 bits are processed. 14 bits (~20 electrons per ADU) provides good sampling of the FPA read noise, full coverage of the full detector dynamic range and some margin to allow for mismatch between the DC outputs of the various FPA readouts.
The analog chain for the MIPS 24 micron array is similar to the Ge:Ga analog chain shown above. Four identical analog chains are provided for this array. A differential receiver provides common mode rejection for the incoming signal. A two-pole filter is used to limit the bandwidth of the incoming signal. The filter bandwidth for this array is set at 40KHz due to the higher pixel sampling frequency. Four separate ADCs are provided within the IRS electronics to digitize the pixel data. The digitized pixel data from the ADCs are merged and fed into the RAD6000 instrument processor.
A hardware timing generator is used to produce the clock signals for the two MIPS Ge:Ga arrays, synchronization signals for the MIPS Si:As array, and deflection waveforms for the scan mirror. Synchronizing signals are fed from the MIPS timing generator to the IRS timing pattern generator, which produces the actual Si:As array clocking patterns. Both of these timing generators are implemented in hardware with no real time intrusions required by the instrument processor. The MIPS flight software controls the operation of these timing generators through register writes. In operation, the MIPS germanium FPAs will be read out at a frequency of 8Hz and the Si:As array at 2Hz.
Drivers are provided in the MIPS electronics for the array calibration stimulator sources and the thermal anneal heaters. The timing generator produces the stimulator flash pulses, which are synchronized with the array readout. The thermal anneal heater timing is controlled directly by the instrument processor.
The CSMM is controlled by a type I analog servo system. The actual CSMM deflection angle is continuously monitored and compared with the commanded angle. The error signal between the actual and desired positions is integrated and used to drive the CSMM actuator. Mirror deflection commands are generated digitally by the timing generator and converted to an analog command using a digital to analog converter (DAC). The timing generator produces all the required CSMM deflection waveforms including chop waveforms and the sawtooth pattern required by the MIPS scan map mode. The higher currents required by the CSMM and by the array thermal anneal heaters are carried to the cold instrument over a cable constructed of phosphor bronze wire.
Software
The diagram below shows the flow of information to and from the MIPS instrument. As shown in the figure, operational parameters are converted into the appropriate command blocks at the ground station, which are then uplinked to SIRTF. Instrument specific commands are received and distributed by the spacecraft command and data handler (S/C C&DH). The spacecraft C&DH provides the interface between the SIRTF spacecraft and the SIRTF instruments. The spacecraft C&DH sends the MIPS specific commands on to the MIPS processor where they are interpreted and executed by the Control Section Flight Software. Engineering and science data are gathered by the various components of the MIPS embedded flight software and downlinked, via the spacecraft processor, to the ground for processing.
When power is applied to the main electronics of the MIPS instrument, the MIPS processor begins execution of the boot state flight software. The functions for the boot state software are:
- Provide the ability to upload and download data to/from the Error Detection and Correction / Electrically Eraseable Programmable Read Only Memory (EDAC/EEPROM) memory areas from/to the ground system via the S/C C&DH.
- Provide the ability to transfer the code from the EEPROM memory area into the EDAC RAM.
- Provide the ability to begin execution of the Operate state software at an uplinked address location.
- Provide the ability to monitor and output a subset of the full complement of engineering data indicating the current state of the instrument.
- Collect detector, memory dump, and diagnostic data telemetry.
To protect this basic upload and transfer capability, the flight software necessary to perform the boot state software functions resides in a write protected area of radiation hardened EEPROM. To reduce the complexity and increase the reliability of the boot state flight software, it has been written without incorporating the real-time operating system that is being utilized by the operate state flight software. The boot state flight software utilizes a basic cyclic executive to handle its operations.
After the boot state software has copied the operate state software from EEPROM to EDAC RAM, the instrument may be commanded into the operate software state where instrument science activities can be performed. All instrument calibrations, science observations and instrument diagnostic activities are performed by the operate state software. To accomplish this, the operate state software supports the following tasks:
- Configure and operate the MIPS detectors.
- Configure and operate the MIPS scan mirror.
- Configure and control the MIPS instrument stimulators.
- Collect detector, memory dump, and diagnostic data telemetry.
- Collect and monitor engineering data and scan mirror position data.
- Format and output science data to the RS-422 Serial interface.
- Format and output engineering telemetry data to the RS-422 Serial interface.
Multiple sequential observations may be performed while the instrument is in the operate state.
The Control Section Flight Software is written in the 'C' programming language and the operate state flight software utilizes the VxWorks Real-Time Operating System. The flight software was originally developed on a Motorola 603e PowerPC target processor, and will be ported to the Lockheed-Martin RAD-6000 flight processor for final integration and test. The PowerPC development environment is architecturally identical to the RAD-6000 environment with a much lower cost.
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